1. Technical Field
This invention generally relates to output circuits for integrated circuits, and more specifically relates to a driver circuit that is self-timed by the occurrence of data, thereby passing data to the output without requiring a clock edge.
2. Background Art
Many modern electronic circuits require output drivers to selectively output a data signal at a desired time. Many known output drivers include an output data latch driven by a data signal, and a three-state output buffer driven by an output enable signal. Data is typically stored on the output latch, and at some later time the output enable signal is asserted to cause the data stored on the output latch to be driven through the three-state buffer to the output of the driver circuit. In this manner, the latching of data in the output latch is relatively non-critical, i.e., it may occur much sooner than needed, since the data is not enabled onto the output until the output enable signal occurs. This type of output driver relieves strict timing constraints on the data signal, but imposes strict timing constraints on the output enable signal, since the output enable signal must occur at the precise time when data is required on the output.
Various related art data latch and driver circuits are known. Examples of these related art circuits are found in U.S. Pat. No. 4,849,658 "Dynamic Logic Circuit Including Bipolar Transistors and Field-Effect Transistors" (issued Jul. 18, 1989 to Iwamura et al. and assigned to Hitachi, Ltd.); U.S. Pat. No. 4,758,739 "Read Back Latch" (issued Jul. 19, 1988 to Ovens et al. and assigned to Texas Instruments, Inc.); and U.S. Pat. No. 4,334,157 "Data Latch with Enable Signal Gating" (issued Jun. 6, 1982 to Ferris and assigned to Fairchild Camera and Instrument Corp.). Each of these related art circuits require a clock edge or an output enable signal to output the stored data at the appropriate time. None of the known related art circuits provide for data to be self-timed, i.e., for data to be output without requiting an additional timing edge.
Many related art driver circuits thus have outputs gated by the output enable signal, placing the output enable signal in the critical access path for data. The occurrence of the output enable signal must have sufficient timing margins to assure proper assertion of data under all possible circuit conditions, including variations caused by changes in temperature, load, and power supply voltage. The result of these timing margins is that the output enable signal is typically delayed from the occurrence of data, which slows down system operation if data could otherwise be used earlier.
Output driver circuits are common in modern computer systems. Modern computer systems typically include one or more microprocessors and other circuitry which are coupled to one or more address and data busses. To improve the speed of operation of these systems, the dynamic bus was introduced. A dynamic bus is pre-charged to a certain logic level, then the signals on the bus that are not at that logic level are driven at the opposite logic level at the appropriate time of the bus cycle. For example, a dynamic bus may be pre-charged high at the beginning of the bus cycle, with the appropriate signals being pulled low by the output driver circuits at the appropriate time in the bus cycle. The dynamic bus architecture eliminated the need for the totem-pole output that was typically used to drive the output to either a high or a low state, depending on the state of the data stored on the output latch. With the dynamic bus, if the bus is pre-charged high, the output driver must only pull the bus line low if the data to be driven is low. If the data to be driven is high, the bus line is already pre-charged to the high state, and the output driver need do nothing. In like manner, if the bus is precharged low, the output driver need only pull the bus line high if the data to be driven is high.
The related art practice of putting the output enable signal in the critical access path for all bus cycles slows down the operation of the related art drivers when coupled to a dynamic bus. Therefore, there existed a need to provide a driver which is self-timed for most bus cycles, passing through data when data occurs without waiting for a subsequent timing edge, while also allowing for data to be gated by a later assertion of the output enable signal when necessary.